This application claims priority under 35 USC 119 to S.N. 98402460.4, filed in Europe on Oct. 6, 1998 (TI-27688EU) and S.N. 98402455.4, filed in Europe on Oct. 6, 1998 (TI-28433EU).
The present invention relates to the verification of instruction parallelism in a processing engine. In particular, the invention relates to a processing engine providing a verification of instruction parallelism, and to a method of verifying instruction parallelism in a processing engine.
In a processing engine providing parallel instruction execution, there is the potential for resource conflicts to occur. Resource conflicts can result from two instructions requiring the use in parallel of a common resource, such as a register, an arithmetic unit, a bus, a memory location, and so on.
In order to avoid resource conflicts, it would be desirable to establish certain rules for parallel instructions to be valid. These rules need to be obeyed when compiling instructions for execution. However, it would further be desirable to verify the validity of parallelism of the instructions prior to execution to avoid conflicts at runtime.
There is a need to provide a validation methodology that can provide robustness and predictability of operation. Preferably, systematic debugging should be possible to take account of possible illegal combinations of instruction.
The present invention seeks to provide a method and a mechanism for verifying the validity of the instruction parallelism.
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Combinations of features from the dependent claims may be combined with features of the independent claims as appropriate and not merely as explicitly set out in the claims.
In accordance with a first aspect of the invention, there is provided a processing engine for executing instructions in parallel. The processing engine includes an instruction buffer for holding at least two instructions with a first instruction in a first position (e.g., for a lower program address) and a second instruction in a second position (e.g., for a higher program address). Decoding logic provides for decoding of the first instruction for generating first control signals and decoding of the second instruction for generating second control signals. Arbitration logic is operable to arbitrate between the first and second control signals for controlling parallel execution of the instructions in accordance with a set of parallelism rules.
The provision of first and second decoders for the first and second instructions, in combination with the arbitration logic, provides a structure for decoding instructions and processing those instructions in accordance with parallelism rules and enables effective and efficient decoding of instructions with avoidance of resource conflicts.
The operation of the arbitration logic in the processing engine hardware enables a robust and predictable validation methodology to be implemented. As this arbitration logic forms part of the processing engine hardware, a predictable programming model behavior can be achieved. In the case where an illegal instruction pair attempts to execute, integrated validation in an embodiment of the invention can result in at least partial execution occurring in a predictable manner.
The first and second control signals can include respective validity signals indicative of the validity of the first and second instructions in the first and second positions, respectively. The arbitration logic can include data address generation control signal arbitrating logic for arbitrating between the first and second validity signals. The first and second control signals can also include respective first and second data address generation control signals. The data address generation control signal arbitration logic can also be operable to arbitrate between the first and second data address generation control signals according to the set of parallelism rules.
The data address generation control signal arbitration logic is operable selectively to cause inhibiting and/or modifying of the effect of the data address generation control signals dependent upon the result of the data address generation control signal arbitration. In particular, the data address generation control signal arbitration logic can be operable to generate a false condition signal in response to detection of a data address generation control signal combination which is invalid in accordance with the parallelism rules. A conditional execution unit can be responsive to the false condition signal to inhibit and/or modify application of the data address generation control signals.
Data address generation control signal merge logic can be provided for generating merged data address generation control signals from the first and second data address generation control signals.
A data address generating unit can be responsive to the first and second and/or the merged address generation control signals.
The first and second control signals can also include first and second resource control signals, respectively. The arbitration logic can comprises resource control signal arbitration logic for arbitrating between the first and second resource control signals according to the parallelism rules.
The resource control signal arbitration logic can be operable selectively to cause inhibiting and/or modifying of the effect of the resource control signals dependent upon the result of the resource control signal arbitration. In particular, the resource control signal arbitration logic can be operable to generate a false condition signal in response to detection of a resource control signal combination which is invalid in accordance with the parallelism rules. The conditional execution unit can be responsive to the false condition signal to inhibit and/or modify the effect of the resource control signals.
Resource control signal merge logic can be provided for generating merged resource signals from the first and second resource control signals.
Execution units, such as an arithmetic unit or a program unit, can be responsive to the first and second and/or merged resource control signals.
The resource control signal arbitration logic can be operable to control access to a common bus resource (e.g., a bus to be accesses or an order of bus access) for the first and second instructions. It can also be operable to modify an order of instructions according to the parallelism rules.
The processing unit can, for example, be in the form of a digital signal processor. The processing engine can be integrated in an integrated circuit.
In accordance with another aspect of the invention, there is provided a telecommunications apparatus comprising a processing engine according to any preceding claim. The telecommunications apparatus can include, for example, a user input device, a display, a wireless telecommunications interface and an aerial.
In accordance with a further aspect of the invention, there is provided a method of executing instructions in parallel in a processing engine, which processing engine comprises an instruction buffer for holding at least two instructions with a first instruction in a first position (e.g., for a lower program address) and a second instruction in a second position (e.g., for a higher program address). The method includes steps of:
a) decoding the first instruction and generating first control signals;
b) decoding the second instruction and generating second control signals; and
c) arbitrating between the first and second control signals for controlling parallel execution of the instructions in accordance with a set of parallelism rules.